This disclosure relates to frequency synthesizers that can be implemented in wireless communication devices, and more particularly to phase locked loop (PLL) circuits of frequency synthesizers.
Frequency synthesizers are commonly implemented within wireless communication devices that transmit and receive encoded radio frequency (RF) signals. A number of different wireless communication techniques have been developed including frequency division multiple access (FDMA), time division multiple access (TDMA) and various spread spectrum techniques. One common spread spectrum technique used in wireless communication is code division multiple access (CDMA) signal modulation in which multiple communications are simultaneously transmitted over a spread spectrum radio-frequency (RF) signal. Some example wireless communication devices that have incorporated one or more wireless communication techniques include cellular radiotelephones, PCMCIA cards incorporated within portable computers, personal digital assistants (PDAs) equipped with wireless communication capabilities, and the like.
Frequency synthesizers of wireless communication devices may be used during both RF signal reception and RF signal transmission. For example, during RF signal reception of CDMA modulated signals, received RF signals are typically mixed down to baseband signals, which can be converted to digital values. During the mixing down process, reference waveforms are produced by a frequency synthesizer and used to remove the RF carrier component from the received signal. The reference waveforms are sometimes referred to as local oscillator (LO) signals. After mixing the RF signal down to baseband, the baseband signals are typically passed through an analog-to-digital (A/D) converter to produce the digital values that can be tracked and demodulated. For example, a RAKE receiver can be used to track and demodulate multi-path signals of a CDMA system. A number of different CDMA architectures have been developed, such as for example, a heterodyne architecture that includes both an intermediate frequency (IF) section and an RF section, and a Zero IF architecture which converts incoming RF signals directly into baseband signals without first converting the RF signals to IF signals. Depending on the architecture, any number of frequency synthesizers may be implemented to provide reference waveforms to the mixers.
Frequency synthesizers are also used during RF signal transmission. In that case, baseband signals are up-mixed to RF. During the up-mixing process, the frequency synthesizer produces carrier RF waveforms. The carrier waveforms are then mixed with the baseband signal before being transmitted. The frequency synthesizer may include a voltage controlled oscillator (VCO) whose frequency is controlled and adjusted by a phase locked loop (PLL). The timing reference for the PLL is typically a high precision low frequency crystal oscillator, such as a voltage controlled temperature compensated crystal oscillator (VCTCXO).
Phase locked loops (PLLs) generally operate by measuring the output frequency of the VCO, and providing closed loop feedback to the input signal of the VCO. For example, a frequency divider can be used to divide the output signal of the VCO by an integer value. The divided value can then be compared to a higher precision low frequency timing reference. Adjustments can be made to the input voltage applied to the VCO so that the output converges to the desired value.
In order to improve the amount of resolution in a PLL, circuits have been developed that generate fractional division factors, on average. For example, the division factor used by the frequency divider can be generated by a xcexa3xcex94 (sigma-delta) modulator. Such a PLL is sometimes referred to as a xcexa3xcex94-controlled PLL. The xcexa3xcex94 modulator generates different division factors for each iteration of loop, so that on average, a fractional division factor can be represented in the PLL.
In order to avoid repetitive cycles in a xcexa3xcex94-controlled PLL, a pseudo-random signal can be introduced to the xcexa3xcex94 modulator. This pseudo-random signal is sometimes referred to as a dither or a dithering signal. The introduction of the dithering signal may help ensure that the xcexa3xcex94 modulator does not fall into a limit cycle in which the division factors generated by the xcexa3xcex94 modulator begin repeating in a cyclical pattern.
In one embodiment, a frequency synthesizer for use in a wireless communication device is described. For example, the frequency synthesizer may include an oscillator and a xcexa3xcex94-controlled phase-locked loop (PLL) that determines and controls the output frequency of the frequency synthesizer.
The xcexa3xcex94-controlled PLL may implement a dithering signal generation technique that can reduce or eliminate the introduction of an average frequency offset (also referred to as a dithering offset). In particular, a dithering signal generator may generate a dithering signal from two or more dithering components. At least one of the dithering components may comprise a component used in the generation of a previous dithering signal.
For example, generation of the dithering signal may include generating a new dithering component and subtracting the component used in the generation of the previous dithering signal from the new dithering component. In this manner, the introduction of an average frequency offset can be substantially avoided because each time a new dithering component is introduced, it is subsequently removed in a later clock cycle.
The various embodiments and techniques described in detail below may be implemented in hardware, software, firmware, or any combination thereof. Additional details of these and other embodiments are set forth in the accompanying drawings and the description below. Other features, objects and advantages will become apparent from the description and drawings, and from the claims.